The KIPS architecture is a simple 16-bit word-addressed RISC microprocessor architecture designed for use in embedded systems, patterned somewhat after the MIPS architecture. It was designed by Damian Yerrick and [Jon Gilpin]? at [Rose-Hulman Institute of Technology]?, presumably as a final project in Rose's CS232, Computer Architecture. |
This page once held a lame attempt to parallel MIPS architecture when somebody wrote about another meaning of KIPS. I have since realized that it doesn't merit an encyclopedia entry. |
The instruction set is designed for somewhat easy assembly language coding. A simulator and disassembler are provided with the development kit; these are released as free software. The reference assembler is still in development. External signalsThe existing implementation of the KIPS architecture uses a 16-bit address bus and 16-bit data bus and can address up to 65,536 16-bit words of memory. The other pins include CLK, /RESET, PWR, and GND. The initial processor has no interrupt pull lines. When the system starts, it jumps to address 0, which generally contains a long jump (lui, or, jr) to the initial program. Future versions may jump to other low-numbered addresses when they receive an interrupt. A simulator can represent the memory and registers thus:
Registers and calling conventionsKIPS has eight registers:
Instruction formatsThe KIPS architecture's 16-bit instructions are laid out on this general plan:
Or, in more detail:
The initial implementation uses a multicycle datapath. Cycle-by-cycle descriptions of the initial implementation follow each instruction's description. Cycle operations: before decodingCycle 1: instruction = mem[pc]; pc += 1; Cycle 2: a = reg[instruction[b..9]]; b = reg[instruction[8..6]]; aluout = pc + sex(instruction[8..0]); This leaves the branch destination in aluout. Detailed descriptions of instructionslet and leti (8 instructions)The let family of instructions performs ALU functions on numbers contained in registers, or a register and an immediate value in [-256..255]. The function codes are as follows:
*Initial prototypes do not contain the shl instruction because of the difficulty of modeling a [barrel shifter]? in Capilano DesignWorks?. Five of these operations (sub through and) have the same function codes as the corresponding operations on the standard 74LS382? ALU. The let instruction puts the contents of two registers through the ALU and stores the result in another register, which may be the same as one of the source registers. On the other hand, leti instructions always store their result in the source register; this leaves nine bits for the immediate value, allowing both unsigned 8-bit bytes and signed values to be specified in one instruction. For example, the forms of the add instruction are
Other let-family instructions are similar. Cycle operations: letCycle 3: aluout = func(a, b); Cycle 4: reg[instruction[5..3]] = i; Cycle operations: letiCycle 3: aluout = func(a, sex(instruction[8..0])); Cycle 4: reg[instruction[b..9]] = i; lui (1 instruction)li can load any immediate value between -256 and 255 into a register.
An assembler will change an out-of-range li into an lui/or pair. Cycle operations: lui3: reg[instruction[b..9]] = instruction[7..0] << 8; lw and sw (2 instructions)
Cycle operations: lwCycle 3: aluout = sex(ir[5..0]) + b; Cycle 4: memdata = mem[aluout]; Cycle 5: reg[instruction[b..9]] = memdata; Cycle operations: swCycle 3: aluout = b + sex(ir[5..0]); Cycle 4: mem[aluout] = a; jl (1 instruction)
Cycle operations: jlCycle 3: reg[instruction[b..9]] = pc; pc = aluout; jr (1 instruction)
Cycle operations: jrCycle 3: pc = a; bz and bnz
Cycle operations: bnzCycle 3: if(a != 0) pc = aluout; Cycle operations: bzCycle 3: if(a == 0) pc = aluout; Want more?If you so request (on Damian Yerrick's whiteboard), Damian may post more information. :What if we want less? In all seriousness, is a CompArch? processor worth an _encyclopedia_entry_? -- EdwardOConnor ::Of course it is ! That's why Wikipedia is so much better than paperpedias. --Taw :::Maybe you don't understand. This "KIPS architecture" is the result of a sophomore-level required project. Thousands upon thousands of CS and ECE students the world over design toy processors like this for class every year. I don't think that we should have an encyclopedia article on each and every one, and this particular exemplar isn't distinguished from the rest in any remotely significant way. So next Fall, will Damian write an encyclopedia article on the Scheme interpreter he'll be required to write in CS304? This strikes me as absurd. This is like someone posting an essay (written for a sophomore-level Philosophy class) on their own personal take on epistemology, in an article called "KIPS epistemology" or some such. -- EdwardOConnor ::::You mean that such processor doesn't exist in hardware ? In that case ... --Taw :::::Right. So, what should be done? Surely, the content is good, it just doesn't seem to fit into the idea that Wikipedia is an encyclopedia. -- EdwardOConnor ::::::I've gotta agree with Ted (EdwardOConnor). Maybe we could move this article, temporarily, to Wikipedia commentary. (And thence probably to a special section of the metawiki which will probably exist soon.) --LMS |
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