First, the PDP-11 was designed from the ground-up to be produced in a factory by semiskilled labor. All of the dimensions of its backplane were relatively noncritical. All parts of the computer chassis were constructed from injection-molded plastic, or bent steel rod (lighter than sheet metal). It used a push-bonded backplane constructed by pushing wires into standard connector blocks that were very similar to telephone connection blocks. The case was injection-molded plastic that fit over the steel-rod chassis.
The CPU's microcode included a debugger that directly communicated to a standard RS-232 terminal. Thus, if the CPU worked, it was possible to examine and correct the computer's internal state. This avoided the expense and inconvenience of a switch array, which was then the typical way to enter digital data into a near-dead computer.
The microcode also included a generic bootstrap, to which all DEC disk drives were compatible.
These two innovations meant that most of the time, the computer just worked. If it didn't boot from its big disk, it would boot from its floppy. If the hardware worked at all, it talked to you through a terminal in a familiar way.
The instruction set was one of the most orthogonal ever designed. Each instruction separated into two six-bit address modes and a four-bit op-code. All op-codes operated with any combination of address modes.
There were 8 general-purpose registers numbered 0 through 7. Any register could be used for most purposes, although register 7 was elected as the stack pointer for subroutines.
In the most radical departure from other, earlier computers, the PDP-11 had no dedicated bus for input/output. It had only a memory bus. All input and output devices were mapped to addresses in memory.
The interrupt and bus was intentionally designed to be as simple as possible, while assuring that no event in an interrupt sequence could be missed. A device would request an interrupt by asserting an interrupt daisy chain. The daisy chain order established the priority of the device. When the CPU responded, the device would place its vector on the bus. The CPU would then load the status register and starting address from the vector table, and temporarily disable interrupts. The interrupt code would then service the device, and in the process, turn off the interrupt signal. Finally, a special RTI (return from interrupt) instruction would enable interrupts on all devices. Note that this process prevents loss of interrupts. At every stage, if the interrupt is not serviced, it remains in place, to be sensed on the next cycle. If a sequence is erroneousl started, the CPU would time out, generating a spurious interrupt. The spurious interrupt would warn users of bad hardware.
The address modes included: 1. Immediate- the value is from the code 2. Register-direct- the value is to or from a register 3. Reigster-indirect- register is used as a memory address to read or write 4. Register indirect with predecrement- as in 3, but it's decremented first. 5. Register indirect with post-increment- as in 3, but it;s incremented afterwards. 6. Register indirect with an offset- as in 3, but an offset is added before using it. 7. Memory direct- an address in memory is accessed. [I seem to remember that the 8th was some sort of indexed access, but I can't remember.]
The instructions were totally generic: add, adc (add with carry), sub, subb (subtract with borrow), mov (moves from anywhere, to anywhere), and, or, not, jmp, jsr, jcc: where cc was some test of the bits in the status register.
The status register included bits for Carry, Zero and Negative.
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