The DataEncryptionStandard (DES) is a product block CipheR in which 16 iterations, or rounds, of the substitution and transposition (permutation) process are cascaded. The block size is 64 bits, so that a 64-bit block of data (plaintext) can be encrypted into a 64-bit cipher at any one time. (A 64-bit block cipher can be decrypted by the DES as well.) The key, which controls the transformation, also consists of 64 bits. Only 56 of these, however, are at the user's disposal; the remaining eight bits are employed for checking parity (the state of being odd or even used as a basis for detecting errors in binary-coded data). Figure 7 is a functional schematic of the sequence of events that occurs in the DES encryption (or decryption) transformation. Subsets of the key bits are designated K1, K2, etc., with the subscript indicating the number of the round. The CipheR function (substitution and transposition) that is used with the key bits in each round is labeled f. At each intermediate stage of the transformation process, the CipheR output from the preceding stage is partitioned into the 32 leftmost bits, Li, and the 32 rightmost bits, Ri. Ri is transposed to become the left-hand part of the next higher intermediate CipheR, Li+1. The right-hand half of the next CipheR, Ri+1, however, is a complex function of the key and of the entire preceding intermediate cipher. The essential feature to the security of the DES is that f involves a very special nonlinear substitution--i.e., f(A) + f(B) f(A + B)--specified by the Bureau of Standards in tabulated functions known as S boxes. This operation results in a 32-bit number, which is logically added to Ri to produce the left-hand half of the new intermediate CipheR. This process is repeated, 16 times in all. To decrypt a CipheR, the process is carried out in reverse order, with the 16th round being first. The DES process lends itself well to integrated-chip implementation. By 1984 the Bureau of Standards had certified over 35 LSI- and VLSI-chip implementations of the DES, most on single 40-pin chips, some of which operate at speeds of several million bits per second.