History of RISC

	Revision 6 . . (edit) December 14, 2001 1:19 am by Uriyan
	Revision 5 . . (edit) December 14, 2001 12:05 am by (logged).253.64.xxx
	Revision 4 . . November 30, 2001 12:21 pm by GregLindahl
	Revision 3 . . November 7, 2001 6:47 am by WojPob [added foldoc]

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Difference (from prior major revision) (minor diff, author diff)

Changed: 3c3

A processor? whose design is based on the rapid execution of a sequence of simple instructions rather than on the provision of a large variety of complex instructions (as in a Complex Instruction Set Computer).

A processor? whose design is based on the rapid execution of a sequence of simple instructions rather than on the provision of a large variety of complex instructions (as in a [Complex Instruction Set Computer]?, or CISC).

Changed: 7c7

Examples of (more or less) RISC processors are the Berkeley RISC, HP-PA, Clipper, i960, AMD 29000, MIPS R2000 and DEC Alpha. IBM's first RISC computer was the RT/PC (IBM 801), they now produce the RISC-based RISC System/6000 and SP/2 lines.

Examples of (more or less) RISC processors are the Berkeley RISC, HP-PA, Clipper, i960, AMD 29000, MIPS R2000 and DEC Alpha. IBM's first RISC computer was the RT/PC (IBM 801), they now produce the RISC-based RISC System/6000 and SP/2 lines. Seymour Cray's vector machines are arguably RISC processors.

Changed: 19c19

There are a number of differences between 'typical' pre-RISC ISAs and 'typical' RISC ISAs. One of these is the addition of an instruction immediately following a jump or branch, which capitalizes on the fact that the processor may take more than one cycle to complete the jump instruction, and allows the program's implementor to use the lookup time more efficiently.

There are a number of differences between 'typical' pre-RISC ISAs and 'typical' RISC ISAs. One of these is the "brancy delay slot": an instruction immediately following a jump or branch, which capitalizes on the fact that the processor may take more than one cycle to complete the jump instruction, and allows the program's implementor to use the lookup time more efficiently.