The MIPS CPU family was one of the most successful and flexible CPU designs throughout the 1990s and has found broad application in [embedded systems]?, [Windows CE]? devices, SGI workstations, and Cisco? Internet routers. The Nintendo 64 video game console uses a 64 bit MIPS processor.
The MIPS CPU features a five stage [CPU pipeline]? to execute multiple instructions at the same time. The CPU has 32 registers, from which two serve special purposes, the rest being available to generic use, regulated through ABI? conventions. Popular compilers that target the MIPS architecture include the MIPSPro Compiler and GCC. Four backward-compatible revisions of the MIPS [instruction set]? exist, named MIPS I to MIPS IV. Because the designers created such a clean instruction set (see /Instructions?), computer architecture courses in universities and technical schools often study the MIPS architecture. The design of the MIPS CPU family, together with SPARC?, another early RISC architecture, greatly influenced later RISC designs like [HP Precision Architecture]? and Alpha.
The early MIPS architectures were 32 bit implementations (generally 32 bit wide registers and data paths), later versions were 64 bit implementations.
In 1984, researchers at Stanford University created the first MIPS processor. The first commercial MIPS CPU, model R2000, was released in 1985. In 1987 the successor, the R3000 CPU was released. It had cache design problems and led to the development of the R4000 and R6000 MIPS CPU series. The R4000 CPU turned out to be a commercial success when introduced in 1991. It had features that broke new ground: a true 64 bit architecture, a real 64 bit [instruction set]? and 64 bit registers, huge on-die? caches, and high clock frequencies. Later designs reused the R4000 core, namely the R4400 (1993), R4600 (1993) and R4300 (1995) CPUs. In 1996, MIPS introduced the R10000 CPU for high-performance applications and the low-power, inexpensive R5000 CPU suited for [embedded systems]?.
This book about computer design in general, and RISC in particular takes its examples directly from the MIPS architecture. No wonder, since Hennessy was an early collaborator in the Stanford project which became MIPS.
![[Home]](wikipedia.png)